This present invention relates generally to computer memory, and more specifically to constrained coding to reduce floating gate coupling in non-volatile memories.
Phase-change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, program/erase cycles for flash memory), the memory cells wear out and can no longer reliably store information.
Not-and (NAND) flash memories are widely used in contemporary memory systems due to their relatively low cost and high density. One source of errors in NAND flash memory is the capacitive coupling between adjacent floating gates that may cause cell-to-cell interference between adjacent cells in a NAND flash memory block. This type of potential error is of increasing importance with the increasing prominence of multi-level cells with increasing numbers of storage levels, and with the decreasing size of flash memory cells. Both the increasing number of storage levels and the decreasing size of flash memory cells improve storage density. As described in the article “A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories” by Park et al., in the April 2008 IEE Journal of Solid-State Circuits, floating-gate coupling may be the dominant cause of errors for small multi-level cell (MLC) flash devices.
Contemporary flash memory controllers use error correction coding (ECC) to correct up to a certain number of bit errors per page. However, such ECC is limited, and can only correct a few bit errors per data block (for example, it may correct up to 12 bits per 512 bytes of data). Given the limitations on ECC, restrictions may be imposed on how writing to a NAND flash block may be performed. For example, MLC memories may restrict the user to sequential writing of pages in a block, with only one write allowed per page. Restrictions such as this can cause an increase in write latency, and can also cause write amplification. Write amplification adversely affects the lifetime of the flash device due to the wear caused by the additional program/erase cycles.